The present invention relates to processor control of an electronic device, particularly to a performance on demand processor resource allocation method in an electronic device, and an associated apparatus.
According to the related art, as the progress of modern electronic devices, the CPU topology changed dramatically and also the diversity increased. For example, from symmetric multi-processor (SMP) to heterogeneous multi-processor (HMP), asymmetric multi-processor (AMP), and even hybrid architecture, developed for system flexibility, power efficiency, thermal strategy, product differentiation, etc. Compared with SMP, these non-SMP topologies are typically composed of asymmetric CPUs variant on physical characteristics, including micro-architecture, computing capability, and power efficiency. These physical variances between asymmetric non-SMP CPUs challenge traditional technologies of SMP hot-plugging and dynamic voltage and frequency scaling (DVFS) dramatically.
Conventional hot-plugging and DVFS, originated from SMP systems, are designed to adjust the number of active cores and the associated operating frequencies according to the system loading. For example, if the system loading is higher than a certain threshold, one or more cores may be plugged and frequency up-shifting may be performed. If the system loading is lower than a certain threshold, one or more cores may be un-plugged and frequency down-shifting may be performed. But SMP systems will not consider which cores to adjust, since all cores are not differentiated. On a non-SMP system, to balance between performance and low-power, decision making of hot-plugging and DVFS may become more complex. In addition, on a HMP, a bigger core may have better performance with higher power cost, while a smaller one may have more balanced power efficiency. According to physical characteristics, two small cores may provide the same computing capability as one big core, but with less total power consumption. However, a task is not always dividable, and the performance of running on one of the two small cores may be half of (or less than) that of the one big core. Therefore, performance and low-power balance may have become an important issue on modern mobile devices, especially on an asymmetric system. For example, choosing a wrong class of CPU may result in terrible user experience or unnecessary system power waste. The disclosed implementation method and the associated apparatus may be applied to one or a combination of various types of processor resources, such as the SMP architecture that typically has multiple cores with the same DMIPS (i.e. Dhrystone Million Instructions Per Second (MIPS)) and operating frequency (e.g. in unit of megahertz (MHz)), the HMP architecture that typically has multiple cores with different DMIPS and operating frequencies and different power consumption, and the AMP architecture that typically has multiple cores with the same DMIPS, but different operating frequencies or different manufacturing processes.
FIG. 1 is a diagram of a conventional method in the related art. For example, the conventional method may comprise processor resources 110 including a plurality of processor cores (e.g. central processing unit (CPU) cores), examples of which may comprise the processor cores CPUX, CPUZ, CPUY, CPUL, and CPUT shown around the upper most of FIG. 1. A processor core depicted with dashed lines indicates that this processor core is hot-unplugged (e.g. the power thereof may be temporarily turned off). A processor core depicted with non-dashed lines indicates that this processor core is hot-plugged (e.g. the power thereof may be temporarily turned on) and operated in its full or partial capability, depends on the ratio of non-dashed lines compared to dashed lines. The shaded content(s) depicted in a processor core indicates the working load of this processor core compared to its computing capability. The statuses of the processor cores may vary from time to time.
According to the related art, the conventional method may operate legacy hot-plug/DVFS method. For example, in the first transition taking around 10 milliseconds (ms) or more, the DVFS operation of the conventional method may up shift the online CPU frequency to a reasonable level (which may be the maximum capability of the online CPU). In the second transition taking around 100 ms or more, when the existing online CPUs cannot handle the overall system loading, the hot-plug operation of the conventional method may strategically enable CPU(s) to ease workload tensions. The strategies of enabling CPUs may be the consideration of most powerful, most power efficient, most power saving, etc. However, the conventional method encounters some problems. For example, the conventional method may be late to response, the independent usage of hot-plugging and DVFS may cause extra delay and response time.
As mentioned, there are some problems in the related art. Thus, a novel method is required to enhance the processor control of an electronic device.